Hi everyone,
I've recently started messing around with FPGAs, and, though this is possibly very naive, wanted to try my hand at digital class D. I found an IEEE paper titled A Class-D Amplifier with Digital PWM and Digital Loop-Filter using a Mixed-Signal Feedback Loop that I wanted to implement on an FPGA. However, the paper prioritizes power efficiency over fidelity, and (from what I can tell) neglects post-filter feedback. I've attached a block diagram illustrating essentially what...
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I've recently started messing around with FPGAs, and, though this is possibly very naive, wanted to try my hand at digital class D. I found an IEEE paper titled A Class-D Amplifier with Digital PWM and Digital Loop-Filter using a Mixed-Signal Feedback Loop that I wanted to implement on an FPGA. However, the paper prioritizes power efficiency over fidelity, and (from what I can tell) neglects post-filter feedback. I've attached a block diagram illustrating essentially what...
Read more